The present invention relates to a pattern inspection apparatus and a pattern inspection method, and more particularly to a pattern inspection apparatus and a pattern inspection method for inspecting fine patterns of semiconductor integrated circuits (or LSI), liquid crystal panels, and their photomasks (reticles) which have been fabricated on the basis of, for example, design data.
An optical pattern inspection apparatus, which uses a die-to-die comparison method, is used for a wafer pattern inspection in a semiconductor integrated circuit manufacturing process or for a pattern inspection of photomask that forms wafer patterns. The die-to-die comparison method is a technique of detecting a defect by comparing an image of a semiconductor device, which is referred to as a die to be inspected, with an image obtained at the same position in an adjacent die.
On the other hand, for the inspection of a photomask (reticle) having no adjacent die, a die-to-database comparison method has been used. In this die-to-database comparison method, mask data are converted into an image. The image is then used for a substitution of the image of the adjacent die used in the die-to-die comparison method, and inspection is performed in the same manner as the above. The mask data are data obtained by applying photomask correction to design data. The technology concerned is disclosed, for example, in U.S. Pat. No. 5,563,702, “Automated photomask inspection apparatus and method.”
However, when the die-to-database comparison method is used for wafer inspection, corner roundness of a pattern actually formed on a wafer is likely to be detected as a defect. In the inspection of a photomask, a pretreatment, which adds corner roundness to the image converted from the mask data by applying a smoothing filter, prevents the corner roundness of the pattern from being detected as the defect. However, in the inspection of a wafer, because the corner roundness added by the pretreatment may be different from corner roundness of each pattern actually formed on the wafer, the pretreatment may not perfectly prevent the corner roundness of the pattern from being detected as the defect. Therefore, an allowable pattern deformation quantity should be set in order to ignore the above difference. As a result, a problem in which a fine defect existing in a place except a corner cannot be detected has happened.
From a viewpoint of problems in semiconductor integrated circuit fabrication, repeated defects (systematic defects) are more important issue than a random defect caused by a particle or the like. The repeated defects are defined as defects that occur repeatedly over all dies on a wafer caused by photomask failure, or the like. Because the repeated defects occur in a die to-be-inspected and in adjacent dies that are to be compared with the die to-be-inspected, the die-to-die comparison wafer inspection cannot detect the repeated defects. Accordingly, the die-to-database comparison wafer inspection has been demanded.
With regard to the number of data required in the die-to-database comparison method for the systematic defects and in the die-to-die comparison method for the random defects, inspection and measurement are carried out until several thousands to several millions or more of data are obtained, in order to statistically express an outcome of a semiconductor process.
However, it is difficult to accurately know, prior to the inspection and measurement, the number of data of several thousands to several millions or more which are required for statistically determining a CD (Critical Dimension) value, a representative value of two-dimensional pattern shape information, or a shape of a frequency distribution of detected defects, or for calculating an incidence rate of defect. For this reason, data, which may be more than necessary, are obtained while the pattern inspection is carried out. For example, a document 1 “Guidelines for measurement sampling properly to maintain and to manage method of semiconductor wafer fabrication processes” refers to the need for increasing the number of data in case a stability of a processing capability is unknown. However, it is difficult to know such a processing capability prior to the inspection and measurement.
The conventional die-to-die comparison method is unable to inspect whether an OPC pattern effectively serves to correct a wafer pattern. Therefore, there has been a demand for its solution, e.g., a technique for comparing and verifying a wafer pattern with design data in consideration of an allowable pattern deformation quantity.
In addition, in a multi-product and small-volume fabricating process, e.g. a system-on-a-chip (SoC) fabricating process, a short delivery time is required. In such a case, if the systematic defect is detected in electric inspection as a final inspection, a short delivery time cannot be achieved. In order to solve this problem, it is necessary to monitor a difference between a pattern formed on a wafer and design data in each stage of the lithography process. Thus, it is necessary for an inspection method to set an allowable pattern deformation quantity that does not affect an electrical property, and to compare and verify design data and a wafer pattern in consideration of deformation within the allowable pattern deformation quantity.
At present, a design check is carried out by a lithography simulator or the like for evaluating pattern deformation. In order to verify the validity of the simulation, it is necessary to prepare a means for comparing and examining a pattern (or a simulation pattern) outputted from the lithography simulator and an actual pattern.
Further, it is more and more important to improve the technology of circuit designing by determining a pattern deformation quantity relative to design data.
In the meanwhile, at present, a CD-SEM (Critical Dimension Scanning Electron Microscope) is used for controlling the pattern width of the wafer in the manufacturing process of semiconductor integrated circuits. This CD-SEM carries out automatic measurement of the line width of a straight line pattern at a specified position using a line profile for each transfer unit of the stepper called a shot. This measurement is performed in several positions for several shots on several pieces of the wafers for one lot, and whether a transfer function of the stepper is normal can be controlled in units of nm (nanometers).
As control items of the circuit pattern, shrink in an endpoint of the wiring, a position of an isolated pattern and the like are also important besides the line width, but the automatic measuring function of the CD-SEM allows only one dimensional measurement. Specifically, the CD-SEM can measure only the length such as the line width. Consequently, the measurement of those two-dimensional shapes is conducted by the operator's visual inspection of the images obtained by the CD-SEM or other microscopes.
The optical proximity effect correction (OPC) plays an important role not only to secure the line width of the straight line pattern but also to form shapes of the corners and isolated patterns. Furthermore, because of improvement of an operating frequency, presently, the control of the shape of a top end or base of the gate wiring pattern, called an endcap or a field extension, respectively, also becomes important in addition to the gate line width.
Such shape measurement of two-dimensional patterns is essential both in the sampling inspection in the manufacturing process and in a trial production phase. Especially in the trial production phase, it is necessary to inspect the pattern formation on the whole wafer.
The automatic length measuring function of the CD-SEM is performed only with a small number of measurement points on the wafer surface, and the measured values cannot be used to provide a representative value of the shape measurement of two-dimensional pattern.
As a result, there is a need for mass CD (Critical Dimension) measurement for measuring several thousand points to several million points or more.
The result of the mass CD (Critical Dimension) measurement is expressed as a frequency distribution, whose shape is not always a normal distribution. Accordingly, it may be difficult to process its statistic as it is. For example, a document 2 “Hot spot management through design based metrology: measurement and filtering” discloses a case where a shape of a frequency distribution of results of mass CD (Critical Dimension) measurement is different from a normal distribution due to the influences of a pattern design.